Note: It is recommended to follow this series of VHDL tutorials in order, starting with the first tutorial .
In the previous tutorial – VHDL Tutorial 16 – we designed a D flip-flop circuit using VHDL.
For this project, we will:
- Write a VHDL program to build a JK flip-flop circuit
- Check the program's output waveform (the digital circuit) with the flip-flop's truth table.
The JK flip-flop with a clear, predefined circuit:
Truth table 
- Note 1: when J=1 and K=1, the Q output always alternates (from 0 to 1 and 1 to 0)
- Note 2: when J=0 and K=0, output Q maintains its previous state
Now let's write, compile and simulate a VHDL program. Then we will get the waveform output and check it with the given truth table.
Before you begin, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 to properly design the project, as well as edit and compile the program and waveform file, including the final output.
Here. We used a behavioral modeling style to write the VHDL program and build the flip-flop circuit because it is the preferred model for sequential digital circuits.
VHDL Program
ieee library;
use ieee.std_logic_1164.all;
JK_flip_flop entity is
port (clk,J,K,prs,clr: in std_logic;
Q: out std_logic;
Qnot: out std_logic);
end JK_flip_flop;
JKFF_arch architecture of JK_flip_flop is
signal nxt_state, prv_state: std_logic;
signal input: std_logic_vector(1 to 0);
to start
input <= J and K;
process(clk, prs,clr) is
to start
if (clr='1′) then
nxt_state <= '0';
elsif (prs='1′) then
nxt_state <= '1';
elsif (clk'event and clk='1′) then
case (input) is
when “10” => nxt_state <= '1';
when “01” => nxt_state <= '0';
when “00” => nxt_state <= prv_state;
when “11” => nxt_state <= no prv_state;
when others => null;
end of case;
end if;
end of the process;
Q <= state_nxt;
Qnot <= no nxt_state;
prv_state <= nxt_state;
end JKFF_arch;
To refresh your memory on how this works, read the first two VHDL tutorials ( 1 and 2 ) in this series.
Then compile the above program, creating and saving a waveform file with all the necessary inputs and outputs listed (and be sure to apply all the different input combinations). Then simulate the project. You should get the following result…
Simulation waveform 
As shown in this figure, there are three cases highlighted in red, green, and blue:
- Case 1: when prs=1 -> Q = 1 and Qnot = 0 (the flip-flop is set)
- Case 2: when clr=1 -> Q=0 and Qnot = 1 (the flip-flop is clear)
- Case 3: when J=1, K=0 and clk=1 – > Q = 1 and Qnot = 0
Be sure to check the different input-output combinations with the truth table provided.
In the next tutorial, we will learn how to build a T flip-flop circuit using VHDL.
