Note: It is recommended to follow this series of VHDL tutorials in order, starting with the first tutorial .
In the previous tutorial, VHDL Tutorial – 21 we designed an 8-bit full adder circuit using VHDL.
In this tutorial, we will:
- Write a VHDL program that builds a 1-bit and 8-bit comparator circuit
- Check program output waveform (digital circuit) with comparator circuit operation
The 1-bit comparator circuit
Truth table
Now let's write, compile and simulate a VHDL program. Then we will get the waveform output and check it with the given truth table.
Before you begin, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 for designing the project. This will ensure that you correctly edit and compile the program and waveform file, as well as the final output.
VHDL Program
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
comparator_1bit entity is
Port (A,B: in std_logic;
G,S,E: std_logic output);
final comparator_1bit;
comp_arch architecture of comparator_1bit is
to start
G <= A and (not B);
S <= (not A) and B;
E <= A xnor B;
final comp_arch;
It may be helpful to review the first two VHDL tutorials ( 1 and 2 ) in this series to refresh your memory on how this works.
Then compile the above program, creating and saving a waveform file with all required inputs and outputs listed (ensuring all different input combinations apply). Then simulate the project. You should get the following result…
According to this figure, the outputs of 'G' and 'E' are highlighted in red and blue respectively for A>B and A=B.
Next, we'll expand this from a 1-bit comparator to an 8-bit comparator. To do this using VHDL, we will employ a behavioral modeling style because it is easier than the other two styles.
The 8-bit VHDL comparator program
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
comparator_8bit entity is
Port (A,B: in std_logic_vector(0 to 7);
G,S,E: std_logic output);
final comparator_8bit;
comp_arch architecture of comparator_8bit is
to start
process
to start
if A=B then
G <= '0';
S <= '0';
E <= '1';
elsif A>B then
G <= '1';
S <= '0';
E <= '0';
elsif A
G <= '0';
S <= '1';
E <= '0';
end if;
end of the process;
final comp_arch;
Simulation waveform
As shown in this figure, the three results are highlighted in red, blue and green, representing A>B, A
This is the final tutorial in this VHDL series. You can find additional programs for different digital circuits online and practice them to get more hands-on experience with VHDL programming. Keep learning and you will keep progressing!
