Note: It is recommended to follow this series of VHDL tutorials in order, starting with the first tutorial .
In the previous tutorial, VHDL-18 we designed a T flip-flop using VHDL.
For this project, we will:
- Write a VHDL program a VHDL program to construct a 4-bit binary counter
- Check the program output waveform (the digital circuit) with the counter truth table
The 4-bit binary counter
Truth table
Now let's write, compile and simulate a VHDL program. Then we will get the waveform output and check it with the given truth table.
Before you begin, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 for designing the project. This will ensure that you correctly edit and compile the program and waveform file, as well as the final output.
VHDL Program
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity counter is
Port (rst,clk: in std_logic;
o: out std_logic_vector(0 to 3));
final counter;
counter's count_arch architecture is
signal count: std_logic_vector (0 to 3);
to start
process(first,clk)
to start
if (rst = '1') then count <= “0000”;
elsif (clk'event and clk = '1') then count <= count + 1;
end if;
end of the process;
o <= count;
final count_arch;
To refresh your memory on how this works, read the first two VHDL tutorials ( 1 and 2 ) in this series.
Then compile the above program, creating and saving a waveform file with all required inputs and outputs listed (ensuring all different input combinations apply). Then simulate the project. You should get the following result…
Simulation Waveform
It can be easily seen from the waveform that when rst=1, the output 'o' is 0 (0000). It then increases in increments with each positive clock edge: 0001(1), 0010(2), 0011(3), etc.
Now, let's build the ascending-descending counter. It has an additional input signal for “up_down”, so that when:
- The up_down = 0 ->, the counter counts from 0, 1, 2, 3,…15, etc.
- The up_down = 1 ->, the counter counts down from 15, 14, 13,… to 0.
The binary up-down counter (4 bits)
VHDL Program
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity counter is
Port (rst,clk,up_dwn: in std_logic;
o: out std_logic_vector(0 to 3));
final counter;
counter's count_arch architecture is
signal count: std_logic_vector (0 to 3);
to start
process(first,clk)
to start
if (rst = '1') then count <= “0000”;
elsif (clk'event and clk = '0') then
if (up_dwn = '1') then count <= count – 1;
else count <= count + 1;
end if;
end if;
end of the process;
o <= count;
final count_arch;
Simulation waveforms
As you can see in this figure, when up_dwn = 0, the count increases in increments with each negative clock edge. So when up_dwn = 1 the count decreases. These examples are highlighted in red and blue, respectively.
In the next tutorial, we will build a binary to gray code converter and a gray code to binary converter using VHDL.
