In the previous tutorial on the basics of VHSlC or VHDL hardware description language, we discussed the design flow and structure of the VHDL program. Now it's time to learn about VHDL programs.
However, please note that the prerequisite for VHDL programming is the fundamentals of digital electronics and digital circuit design. To fully understand these programs, it is important that you first have adequate knowledge of Boolean algebra, logic gates, combinational and sequential logic circuits, etc.
Before you start here, consider doing a quick refresher on the basics of digital electronics.
Let’s start with some standard and easy VHDL programs…
The full adder VHDL program:
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
full_adder entity is
port (a, b, cin: IN STD_LOGIC;
sum, cout: OUT STD_LOGIC);
end complete_adder;
full_adder_arch architecture of full_adder is
to start
sum <= a xor b xor cin;
cout <= (a and b) or (be cin) or (ae cin);
end full_adder_arch;
The 2 to 4 decoder VHDL program:
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
entity2x4 decoder is
port (a, b,: IN STD_LOGIC;
o0,o1,o2,o3 :OUT STD_LOGIC);
end decoder2x4;
decoder_arch architecture of decoder2x4 is
to start
o0 <= (not a) and (not b);
o1 <= ae (not b);
o2 <= (not a) and b;
o3 <= a and b;
end decoder_arch;
The binary to gray code converter VHDL program:
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
BtoG entity is
port (B0,B1,B2,B3: IN STD_LOGIC;
G0,G1,G2,G3: STD_LOGIC OUTPUT);
end of BtoG;
BtoG's BtoG_arch architecture is
to start
G3 <= B3;
G2 <= B3 xor B2;
G1 <= B2 xor B1;
G0 <= B1 xor B0;
end decoder_arch;
The 4-bit parity generator VHDL program:
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
parity_gen entity is
port (B0,B1,B2,B3: IN STD_LOGIC;
p:OUT STD_LOGIC);
end parity_gen;
parity_gen_arch architecture of parity_gen is
to start
p <= B0 xor (B1 xor (B2 xou B3));
end parity_gen_arch;
The programs above present the style of data flow modeling typically used for combinational logic circuits. To write a program for the sequential logic circuit, it is best to use the behavioral modeling style.
Here are some examples of VHDL programs that use the behavioral modeling style.
The 4x1 multiplexer VHDL program:
ieee library;
use ieee.std_logic_1164.all;
mux41 entity is
port (d: in std_logic_vector (0 to 3);
s: in std_logic_vector (0 to 1);
o: out std_logic);
end mux41;
mux41_arch architecture of mux41 is
to start
process (d,s)
to start
case s is
when “00” => o<= d(0);
when “01” => o<= d(1);
when “10” => o<= d(2);
when “11” => o<= d(3);
final case;
end of the process;
end mux41_arch;
The D flip-flop VHDL program (with reset high input active):
ieee library;
use ieee.std_logic_1164.all;
flip_flop entity is
port (clk,Din,rst: in std_logic;
Q: out std_logic;
Qnot: out std_logic);
final flip_flop;
my_flipflop architecture of flip_flop is
to start
process (clk,Din,rst)
to start
if(rst='1′) then
Q <='0';
Qnot <='1′;
elsif(clk'event and clk='1′) then
Q <=Din;
Qnot <= not Din;
end if;
end of the process;
finish my_flipflop;
The 4-bit binary counter VHDL program:
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity counter is
Port (rst,clk: in std_logic;
o: out std_logic_vector(0 to 3));
final counter;
Counter's counter_arch architecture is
signal count: std_logic_vector (0 to 3);
to start
process(first,clk)
to start
if (rst = '1') then count <= “0000”;
elsif (clk'event and clk = '1') then count <= count + 1;
end if;
end of the process;
o <= count;
end counter_arch;
If the circuit is small and simple, you can use the above two modeling styles for the VHDL program. However, if the circuit is large and complex, it is necessary to use the structural modeling style.
In this style, a large circuit is considered an interconnection of smaller components. This occurs because the complete circuit is represented by a set of interconnected components.
Here is an example of a VHDL program that employs the structural modeling style.
The full adder circuit using the half adder and OR gate as components:
IEEE library;
Use IEEE. STD_LOGIC_1164.all;
fulladder IS entity
port (a,b,cin:em STD_LOGIC;
sum, perform: output STD_LOGIC);
fulladder end;
—————————— full adder architecture
fulladder's FA_arch architecture is
—————————– half-adder component
half_adder component is
port (p,q :in STD_LOGIC;
s,cy: STD_LOGIC output);
final component;
—————————— or gate component
or_gate component is
port (p1,q1:in STD_LOGIC;
r1: STD_LOGIC output);
final component;
—————————-
signal s1,c1,c2: STD_LOGIC;
to start
w1: half_adder port map (a,b,s1,c1);
w2: portmap half_adder(s1,cin,sum,c2);
w3: port map or_gate (c1,c2,carry);
end FA_arch;
————————— half adder component program
half_adder entity is
port (p,q: in STD_LOGIC;
s,cy : STD_LOGIC output);
end half_adder;
HA_arch architecture of half_adder IS
to start
s <= px or q;
cy <= peq;
end HA_arch;
—————————- or gate component program
ou_gate entity is
port (p1,q1:in STD_LOGIC;
r1: STD_LOGIC output);
end ou_gate;
or_gate_arch architecture of or_gate IS
to start
r1 <= p1 or q1;
end ou_gate_arch;
To better understand the three modeling styles, let's design a 2 to 4 decoder using all three methods.
The 2 to 4 decoder using data flow modeling style (it's the same as before):
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
entity2x4 decoder is
port (a, b,: IN STD_LOGIC;
o0,o1,o2,o3 :OUT STD_LOGIC);
end decoder2x4;
decoder_arch architecture of decoder2x4 is
to start
o0 <= (not a) and (not b);
o1 <= ae (not b);
o2 <= (not a) and b;
o3 <= a and b;
end decoder_arch;
The 2 to 4 decoder using the behavior modeling style:
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
entity2x4 decoder is
port (I: IN STD_LOGIC_VECTOR(0 to 1);
O: OUT STD_LOGIC_VECTOR (0 to 3));
end decoder2x4;
decoder_arch architecture of decoder2x4 is
to start
process (me)
to start
if I am
when “00” => O <= “0001”;
when “01” => O <= “0010”;
when “10” => O <= “0100”;
when “11” => O <= “1000”;
final case;
end of the process;
end decoder_arch;
The 2 to 4 decoder using the structural modeling style:
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
entity2x4 decoder is
port (I: IN STD_LOGIC_VECTOR(0 to 1);
O: OUT STD_LOGIC_VECTOR (0 to 3));
end decoder2x4;
decoder_arch architecture of decoder2x4 is
——————— AND GATE component ———————-
and_gate component is
port(a, b: in STD_LOGIC;
y: STD_LOGIC output);
final component;
——————- NOT GATE component ———————–
not_gate component is
port(m: in STD_LOGIC;
n: STD_LOGIC output);
final component;
—————– intermediate output signals—————–
signal p,q: STD_LOGIC;
—————- component port mapping ———————-
to start
w1: port map not_gate (I(0),p);
w2: port map not_gate (I(1),q);
w3: port map and_gate (p,q,O(0));
w4: port map and_gate (I(0),q,O(1));
w5: port map and_gate (p,I(1),O(2));
w3: port map and_gate (I(0),I(1),O(3));
end decoder_arch;
——————— AND GATE component program ————–
and_gate entity is
port(a, b: in STD_LOGIC;
y: STD_LOGIC output);
end e_gate;
and_gate_arch architecture of and_gate is
to start
y <= a and b;
end and_gate_arch;
——————- NOT GATE component program —————-
not_gate entity is
port(m: in STD_LOGIC;
n: STD_LOGIC output);
end not_gate;
not_gate_arch architecture of not_gate is
to start
n <= not m;
end not_gate_arch;
As you can see, we can design any digital circuit using any of the modeling styles. It is up to the designer to choose the ideal and most appropriate modeling style to describe the circuit
In the next tutorial, we will describe how to compile, simulate, run, and verify these VHDL programs when using the MAX+II software tool (from Altera).
