Note: It is recommended to follow this series of VHDL tutorials in order, starting with the first tutorial .
In the previous tutorial VHDL Tutorial – 10 we designed half-adder and full-adder circuits using VHDL.
In this tutorial, we will:
- Write a VHDL program to construct half-subtractor and full-subtractor circuits
- Check the program output waveform (digital circuit) with the truth tables for the half subtractor and full circuits
Half subtractor circuit
Truth table
Now, let's write, compile and simulate a VHDL program to obtain a waveform output. Then we will check the waveform output with the given truth table.
Before you begin, be sure to review the step-by-step procedure provided in VHDL Tutorial – 3 to properly design the project, as well as edit and compile the program and waveform file, including the final output.
VHDL Program:
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
half_sub entity is
port (a,b: in std_logic;
dif,bo: std_logic output
);
end half_sub;
sub_arch architecture of half_sub is
to start
dif <= ax or b;
bo <= (not a) and b;
end sub_arch;
Observation:
- The “entity” describes the input-output connections of the digital circuit. As per the circuit given here, you will notice that there are two inputs ('a' and 'b') and two outputs ('dif' and 'bo').
- The “architecture” describes the operation of the circuit, which means how the output is generated from a given input.
To refresh your memory on how this works, read the first two VHDL tutorials ( 1 and 2 ) in this series.
Next, compile the above program, creating a waveform file with all the necessary inputs and outputs listed, and simulate the project. You should get the following result…
Simulation Waveform
Check the 'dif' and 'bo' output waveforms with the truth table provided. For inputs a=1 and b=0, the outputs are bo=0 and dif=1, which are highlighted in the image.
Next, let's move on to the complete subtractor circuit and its design.
Complete subtractor circuit
Truth table
Let's write the VHDL program for this circuit. In the previous tutorial, we designed the full adder circuit using a structural modeling style for VHDL programming. We will use the same modeling style to design the complete subtractor.
We will build the full subtractor circuit using the half subtractor circuit and the “ OR gate ” as components (or blocks). In the circuit diagram you can see that the complete subtractor circuit consists of two half adders and an OR gate.
VHDL Program
IEEE library;
Use IEEE. STD_LOGIC_1164.all;
full_sub IS entity
port (a,b,bin:in STD_LOGIC;
dif,bout : out STD_LOGIC);
end full_sub;
———————– full subtractor architecture ————-
FS_arch architecture of full_sub is
—————————– half adder component————————–
half_sub component is
port (p,q :in STD_LOGIC;
dif,bo: STD_LOGIC output);
final component;
——————— or gate component ————————-
or_gate component is
port (p1,q1:in STD_LOGIC;
r1: STD_LOGIC output);
final component;
—————————-
signal d1,b1,b2: STD_LOGIC;
to start
w1: port map half_sub (a,b,d1,b1);
w2: port map half_sub (d1,bin,dif,b2);
w3: port map or_gate (b1,b2,bout);
end FS_arch;
————————– half subtractor program ————————
IEEE library;
Use IEEE. STD_LOGIC_1164.all;
half_sub entity is
port (p,q: in STD_LOGIC;
dif,bo : output STD_LOGIC);
end half_sub;
HS_arch architecture of half_sub IS
to start
dif <= p xor q;
bo <= (not p) eq;
end HS_arch;
—————————– or gate program ——————————
IEEE library;
Use IEEE. STD_LOGIC_1164.all;
ou_gate entity is
port (p1,q1:in STD_LOGIC;
r1: STD_LOGIC output);
end ou_gate;
or_gate IS or_g architecture
to start
r1 <= p1 or q1;
end or_g;
To compile the above program:
- Create waveform file with all inputs and outputs listed
- Apply the different input combinations
- Save the waveform file and simulate the project
You should get this result…
Simulation waveforms
Compare the results of 'dif' and 'bout' with the truth table provided. In the above diagram, one case is highlighted as a=0, b=1 and bin=0 with the outputs of dif=1 and bout=1.
In the next tutorial, we will learn how to design an 8-bit parity generator and parity checker circuits using VHDL.