SPI has gained a solid role in embedded systems, whether system-on-chip processors, both with state-of-the-art 32-bit processors, such as those using ARM, MIC or Power PC, and with other microcontrollers, such as AVR, PIC, etc. include SPI controllers capable of operating in master or slave mode. Programmable AVR controllers in the system can be programmed using an SPI interface. Chip or FPGA-based designs sometimes use SPI to communicate. Thus, SPI is a common technology used nowadays to communicate with peripheral devices where we want to transfer data quickly and with real-time restrictions. There are many serial interfaces from Morse code telegraphy, RS232, USB, Fire wire, Ethernet and more. Each serial interface offers advantages or disadvantages for many designs, depending on criteria such as required data rate, space availability, and noise considerations.
Serial to Peripheral Interface (SPI) was one such technology developed to replace parallel interfaces so that we don't have to route the parallel bus around the PCB. It provides high-speed data transfer between devices. Motorola was the first company to name SPI for a circuit technique used in the late 1970s in its first 68000-based MCU to connect it to peripheral functions and later adopted by others in the industry. It is the simplicity of the interface and the speed that allows communication or data transfer easily and has made it a popular communication protocol.
The Serial Peripheral Interface is a simple 4-wire serial communication interface used by many microprocessor/microcontroller peripheral chips that allows controllers and peripheral devices to communicate with each other. In serial peripheral interface, data is transferred in/out one at a time and transmits data from master device to/from one or more slave devices over short distances and high speed. It is simply based on an 8-bit shift register that transfers data to a single pin and transfers data to another pin. Another characteristic of SPI is that there is no concept of transferring ownership of the bus, that is, changing the master and there are also no slave addresses. SPI is a much simpler protocol and that is why we can operate it at speeds greater than 10MH compared to TWI. Some of the features that enable the widely used SPI are-
1. Full duplex communication.
2. Higher yield than TWI.
3. Not limited to 8-bit words in case of bit transfer.
4. Simple hardware interface
5. Arbitrary choice of size, content and purpose of messages.
6. Typically low power requirements
7. Slave uses master clock and does not require precision oscillators.
8. Lower power requirements than TWI due to fewer circuits.
However, it would be unfair to compare the TWI serial interface with SPI. Each of them has its area of application depending on the needs of the system, such as some of the features that make TWI as valuable as SPI.
1. Fewer pins in IC packages than SPI
2. Hardware flow control is present
3. It has a different formal standard than the SPI
4. Approach slaves before communication.
Now that we have a brief idea about SPI, let us understand the answers to the questions that why SPI is more preferred in PCB? What are the basic connections and how do they communicate? And finally, what is the future scope of the SPI?
Why SPI is more preferred for PCB
Figure 1: Block image showing how the SPI protocol works
Although it was developed primarily for communication between the host processor and peripherals, a two-processor connection via SPI is also possible. SPI bus is generally only used on PCB. There are many reasons that prevent us from using it outside the PCB area. Firstly, SPI was designed to transfer data between multiple IC chips, at very high speeds. Due to this high speed, the length of the bus lines should not be too long, as the reactance increases and the bus becomes unusable. However, it is possible to use the SPI bus outside the printed circuit board at low speeds, but this is not very practical. Peripherals can be real-time clocks, converters like ADC and DAC, memory modules like EEPROM and FLASH, sensors like temperature sensors and pressure sensors, or some other devices like signal mixer, potentiometer, LCD controller, UART, controller CAN, USB controller and amplifier.
SPI data and control lines and basic connection:
An SPI protocol specifies 4 signal wires.
1. Master Out Slave In (MOSI) – The MOSI signal is generated by the Master, the recipient is the Slave.
2. Master In Slave Out (MISO) – The slaves generate MISO signals and the recipient is the Master.
3. Serial clock (SCLK or SCK) – The SCLK signal is generated by the Master to synchronize data transfers between the master and slave.
4. Master Slave Selection (SS) to Slave Chip Selection (CS) – The SS signal is generated by the master to select individual slave/peripheral devices. The SS/CS is an active low signal.
Sometimes serial Data In (SDI) is used as another name in place of MOSI and Serial Data Out (SDO) for MISO.
Figure 2: Block diagram showing single master single master application in SPI protocol
Among these four logic signals, two of them MOSI and MISO can be grouped as data lines and two others SS and SCLK as control lines.
A master microcontroller can communicate with multiple SPI peripherals. There are 2 ways to configure things:
1. Cascaded slaves or chained slaves
2. Independent slaves or parallel configuration
Chain Slave Configuration
Chain Slave Configuration: In cascade slave configuration, all clock (SCLK) and chip select (CS) lines are connected together. Data flows from the microcontroller to each peripheral and back to the microcontroller. The data output of the previous slave device is linked to the data input of the next one, thus forming a wider shift register. Thus, cascaded slave devices are evidently seen as one larger device and therefore receive the same chip selection signal. This means that only a single SS line is required from the master, rather than a separate SS line for each slave.
Figure 3: Chain slave configuration in SPI protocol
But we must remember that daisy chaining will not work with devices that support or require multi-byte operation.
Independent slave configuration:
This is the typical SPI bus configuration with an SPI master and multiple slaves/peripherals. In this independent or parallel slave configuration,
All clock lines (SCLK) are connected together.
2. All MISO data lines are connected to each other.
3. All MOSI data lines are connected together.
Figure 4: Block diagram showing the SPI bus in slave configuration
Figure 5: Block diagram showing various functional units in the SPI system
Communication at SPI
How does communication work in SPI?
Communication is initiated by the master all the time. The master first sets the clock using a frequency less than or equal to the maximum frequency supported by the slave device. Now, this SPI master controls the data transfer by generating the clock signal (SCLK). The master then selects the desired slave for communication by pulling the chip select (SS) line of that specific slave peripheral to the “low” state and activates the particular slave it wants to communicate with using the slave select signal (SS) . Once the slave is selected, it receives or transmits data via the two data lines. A master, usually the host microcontroller, always provides clock signal to all devices on a bus, whether it is selected or not. Slaves on the bus that have not been activated by the master using its slave select signal will disregard the input clock and MOSI signals from the master and should not trigger MISO. This means that the master selects only one slave at a time.
The usage of each four pins may depend on the devices. For example, the SDI pin may not be present if a device does not require an input (ADC, for example), or the SDO pin may not be present if a device does not require an output (LCD controllers, for example). If a microcontroller only needs to communicate with 1 SPI peripheral or a slave, then the CS pin of that slave can be grounded. With multiple slave devices, an SS signal independent of the master is required for each slave device.
How important is Tri-state production in SPI?
In digital electronics, three-state, three-state, or 3-state logic allows an output port to assume a high-impedance state beyond logic levels 0 and 1, effectively removing the output from the circuit. This allows multiple circuits to share the same output line or lines (like a bus that cannot listen to more than one device at the same time. Most devices/peripherals have three-state outputs, which go to the high impedance state ( disconnected) when the device is not selected. Devices without these tri-state outputs cannot share the SPI bus with other devices, because that slave's chip selection may not be activated.
Now, if a waiting period is required (such as for analog-to-digital conversion), then the master must wait at least that amount of time before starting to output clock cycles. In the SPI master, bits are sent from the MOSI pin and received at the MISO pin. The bits to be shifted are stored in the SPI data register, SP0DR, and the most significant bit (bit 7) is sent first. When bit 7 of the master is shifted through the MOSI pin, a bit from bit 7 of the slave is shifted to bit 0 of the master through the MISO pin. After 8 pulses or clock shifts, this bit will end up in bit 7 of the master. The least significant bit can be sent first by setting the LSBF bit to 1 in the SPI control register. The clock that controls how quickly bits are transferred to SP0DR is the SCLK signal. The frequency of this clock can be controlled by the SPI baud rate register, SP0BR. The SS pin must be low to select a slave. A complete SPI system is shown below.
Figure 6: Overview of Communication in the SPI System with Master and Slave
Figure 7: Diagram showing the SPI Slave structure
A full duplex means that data transmission can occur in both directions during each clock cycle. So, when the master sends a bit on the MOSI line; the slave reads from that same line and the slave sends a bit on the MISO line; the master reads on the same line. Now to do data transfer organized shift registers are used with a certain word size like 8 bits (may be more) in both master and slave. They are connected in a ring. While the master transfers the register value through the MOSI line, the slave transfers the data to its shift register.
The data is usually shifted with the most significant bit of the MSB first, while the new least significant bit of the LSB is shifted into the same register. After changing this register, the master and slave exchanged their register values. Then each device takes this value and does the necessary operation with it (for example, writing it to memory). If there is more data to be exchanged, the shift registers are loaded with new data and the process is repeated. When there is no more data to be transmitted, the master stops the clock. Normally, he rejects the slave.
Figure 8: Block diagram showing hardware configuration for communication between 2 registers
There is a “multi-byte stream mode” available with SPI bus interface. In this mode the master can shift bytes continuously. In this case, slave selection (SS) is kept low until the entire flow process is completed.
SPI devices sometimes use another signal line to send an interrupt signal to a host CPU. Some of the examples of this type of signal are pen interruptions from touch screen sensors, thermal threshold alerts from temperature sensors, alarms issued by real-time clock chips, and audio sound codec headphone jack inserts. a cell phone.
Clock polarity and phase in SPI
Meaning of clock polarity and phase:
Another pair of parameters called clock polarity (CPOL) and clock phase (CPHA) determines the edges of the clock signal at which data is conducted and sampled. In addition to configuring the clock frequency, the master must also configure means of adjusting or defining the clock polarity (CPOL) and phase (CPHA) in relation to the data. As the clock serves to synchronize data communication, there are four possible modes that can be used in an SPI protocol, based on this CPOL and CPHA.
|
Mode |
Clock Polarity (CPOL) |
Clock Phase (CPHA) |
|
SPI_MODE0 |
0 |
0 |
|
SPI_MODE1 |
0 |
1 |
|
SPI_MODE2 |
1 |
0 |
|
SPI_MODE3 |
1 |
1 |
Fig. 9: SPI timing diagram using VHDL
If the clock phase is zero (that is, CPHA = 0), data will be latched on the rising edge of the clock with CPOL = 0 and on the falling edge of the clock with CPOL = 1.
If CPHA = 1, the polarities are reversed. Data is latched on the falling edge of the clock with CPOL = 0 and on the rising edge with CPOL = 1.
Microcontrollers allow you to adjust the polarity and phase of the clock. A positive polarity results in data latching on the rising edge of the clock. However, the data is placed on the data line already on the falling edge to stabilize. Most peripherals, which can only be slaves, work with this configuration. If it is necessary to use the other polarity, the transitions will be reversed.
SPI APPLICATIONS
Full duplex capability makes SPI very efficient for master/slave applications. Some devices use full-duplex mode to implement fast and efficient data flow for applications such as digital audio, digital signal processing, or telecommunications channels. SPI is used to communicate with various peripherals such as
Sensors: Temperature, pressure, ADC, touch screens, video game controllers
Control devices: Audio encoding and decoding, digital potentiometers, DAC.
Camera lenses: Canon EF lens mount
Communications: Ethernet, USB, USART, CAN portable video games
Memory: Flash and EEPROM
Real-time clocks
LCD, sometimes even for managing image data
Any MMC or SD card (including SDIO variant)
For high-performance systems, FPGAs sometimes use SPI to interface as a slave to a host, as a master for sensors, or to flash memory used for initialization if they are SRAM-based.
JTAG is essentially an application stack for a three-wire SPI type, using different signal names. SGPIO is essentially another (incompatible) application stack for SPI designed for specific backplane management activities. SGPIO uses 3-bit messages.
