Bus States
Bus state refers to the signal voltage level on the USB bus, or the conditions that these voltages signify -:
Single terminated zero: This state is also known as SE0. Occurs when D+ and D- are logically low. The SE0 state is used by the bus when entering the Disconnect, Reset and EOP (End of Packet) states.
Single Finished: Also known as SE1. Occurs when D+ and D- are logically high. This state can be considered a complement to the SE0 state. SE1 should never occur as it is an invalid bus state.
Stopped: This state occurs when the bus remains idle or packets are not exchanged. For a full speed device, the voltage across D+ will be more positive than D- while for a low speed device, the voltage across D- will be more positive than D+
Data J and Data K: The data states J and K are used to define the data states as the differential 0 and 1 which refers to the bus states. They are defined by the Differential 0 or 1 state and the bus speed.
Fig. 1: Table listing flip-flop status for differential 0 and differential 1 bus states
Data states are used to describe an event even when the voltages on the data lines are differential. For example, a packet start state exists when the bus changes from the idle state to the K state.
Start of package: Also known as SOP. This state occurs when there is a change from Idle to K state. Each packet transmission starts with SOP.
End of Package: Also known as EOP. This state occurs when the SEO state occurs for two-bit times, followed by a J state for 1-bit times.
Disconnect: A downstream port to which the device is connected enters the disconnected state when an SE0 state lasts at least 2.5 uS.
Connect: A downstream port enters the connecting state when there is an idle state for at least 2.5 uS and no more than 2 mS
Some other states and signs
Keep the signal alive : This signal is represented by a low-speed EOP. The main reason for this signal is to keep the device in an idle state. This signal is sent at least once every millisecond to prevent the device from entering the sleep state.
Suspend state : The device enters the Suspend state when there is no packet exchange or the bus remains inactive for 3 mS. This state was incorporated into USB for energy conservation. In the suspended state, the device must draw no more than 500 uA of current. A suspended device must recognize the reset and resume signal.
Resume: The resume signal is used to wake the device from the suspended state. The Host wakes the device from sleep state, keeping the bus in the K state for at least 20 ms, followed by a low-speed EOP.
Reset state: A device enters the Reset state if SE0 is applied for more than 2.5 uS. Resetting sets the device to its default, unconfigured state.
Detached State: This state occurs when the USB device is disconnected from the Host. In this state, the Host sees both data lines low.
Attached State : This state occurs when the USB device is connected to the Host. The host recognizes this state if it sees D+ or D- high.
Fig. 2: Table listing conditions for USB bus states
Fig. 3: Signal diagram for different USB bus states
Speed identification
In the USB system, the operating speed of the device is detected by checking which data line is pulled. The data line is pulled up to 3.3 V derived from the voltage line. Typically a 1.5 kilo ohm resistor is used for pull-up.
For low speed, the D data line is pulled up. While for full speed, the D+ data line is pulled up. High-speed devices are initially detected as full-speed devices.
Coding scheme
USB employs NRZI (Non Return to Zero Inversion) coding mechanism to encode data on the bus. In NRZI coding, a '1' is represented by no change in level, while a '0' is represented by a change in level. Along with NRZI encoding, bit boost and SYNC field are used for synchronization between host and device.
Fig. 4: Signal diagram illustrating the non-return-to-zero inversion (NRZI) coding scheme
A little stiff
When long series of zeros are transmitted using NRZI, it causes a transition in levels. But when long series are transmitted, no transition occurs according to the NRZI coding scheme. No level transition for too long can confuse the receiver and make it out of sync.
Bit hardening is a process in which a zero is inserted into the raw data every six consecutive bits. Entering zero causes a level transition. The receiver must recognize the filled bits and discard them after decoding the NRZI data.
If no transition occurs in the NRZI signal after six consecutive transitions, the receiver decides that bit hardening was not done and discards the received data.
Fig. 5: Signal diagram showing bit shift in the non-return-to-zero-inversion (NRZI) coding scheme
SYNCHRONIZE field
Bit hardening alone is not enough to take care of synchronization between transmitter and receiver. To keep the transmitter and receiver synchronized, the SYNC field is used. In this mechanism, each packet begins with a SYNC field that allows the receiver to synchronize the clock
For low/maximum speed, the SYNC field is 8 bits: KJKJKJKK. The first k serves as the beginning of the package. For high speed, the SYNC field is 32 bits: fifteen KJ repeats, followed by KK. The alternate Ks and Js provide transitions for synchronization, and the final two KKs mark the end of the SYNC field.
End of package
The end of the packet which is SE0 for 2-bit times followed by state J for 1-bit times marks the end of the packet.
All this is necessary to know about the signal and coding schemes implemented in the USB system. In the final part of the series, selection of a controller chip for developing custom USB-enabled devices is discussed.