As electronic miniaturization has been a constant goal of chip manufacturers, motherboard-based computer/electronic systems were eventually replaced by System-on-Chip (SoC) and Package-on-Package (PoP) ICs. Complex computer systems are now condensed into smartphones and other portable devices. These sophisticated electronic devices and gadgets have an SoC at their heart that manages complete computation and control. The SoC package is comprised of multiple intellectual property (IP) cores. These IP cores come from different chip design companies and vendors.
Scalable, compatible and efficient data communication between multiple IP cores on an SoC has been a challenge. Initially, this was done by chip designers through laborious redesign, compatibility testing, and additional interface design. This approach lacked coherence at first glance, which led to costly future redesigns. One of the widely accepted and viable solutions to this problem was introduced by Arm in 1996 as AMBA protocols.
What is AMBA?
AMBA (Advanced Microcontroller Bus Architecture) is an open and freely available standard for interconnecting and managing IP cores in a System-on-Chip (SoC) IC. It enables the immediate development of multiprocessor chip designs in a modular, reusable and scalable manner. This helps avoid costly redesigns and reduces time to market for integrated designs.
AMBA was first introduced in 1996 with Advanced Peripheral Bus (APB) and Advanced System Bus (ASB) specifications. The second version of AMBA was introduced in 1999 and included Advanced High-Performance Bus (AHB) specifications. AMBA 3 which included Advanced Extensible Interface (AXI), was introduced in 2003. AMBA 4 introduced AXI Coherency Extensions (ACE) in 2010 and AMBA 5, the latest version of AMBA, introduced Coherent Hub Interface (CHI) in 2013.
AMBA bus system
A traditional AMBA-based SoC design uses Advanced System Bus (ASB) or Advanced High-performance Bus (AHB) specifications for high-bandwidth communication with blocks such as the processor, on-chip RAM, memory interfaces, and master DMA bus. Although it uses Advanced Peripheral Bus (APB) for low bandwidth communication with blocks such as UART, GPIO, keyboard, display, timer, etc., SoCs that have a large number of functional blocks or IP cores require point-to-point interconnection that uses Advanced Extensible Interface (AXI) specifications. The AXI bus manages communication using a master-slave protocol and can be easily connected to the APB. There can be multiple AXI masters and slaves sharing a bus.
Cell phones and smartphones that contain SoCs with multiple processor cores sharing a common cache memory require coherence management across the entire memory subsystem. To this end, the ACE specifications were introduced in AMBA 4. The AXI/ACE specifications were redesigned as CHI to manage communication mechanisms in heterogeneous computing systems. In contrast, for signal-based protocol in AXI/ACE specifications, CHI is a packet-based layered protocol that can be extended to communication mechanisms between heterogeneous functional blocks such as Digital Signal Processors (DSP), Graphics Processing Units ( GPU), I/O subsystems, and memory controllers.
AMBA Specifications
AMBA is a set of interconnection protocols. The latest version AMBA 5 includes the following specifications:
- APB : The latest version of Advanced Peripheral Bus (APB) was introduced in AMBA 2.0. This is a simple pipelineless protocol used for master-slave communication with low-bandwidth peripherals. Several peripherals can be connected to a shared bus, which is managed via a bridge (such as the AXI-APB bridge) or directly by a master (processor/controller). In APB specifications, the same set of signals is used to read and write to the bus and no burst data transfer is supported.
- ASB : Advanced System Bus (ASB) is a pipelined protocol for communication mechanisms with high-bandwidth, high-frequency components. It supports burst transfers and multiple bus masters. This bus system supports interconnection between multiple masters and memories. The bus consists of four types of blocks – Master, Arbiter, Slave and Decoder. At any time, only one master can access the bus. A master can only access the bus with the help of an arbiter while it needs to select a slave for communication using a decoder. The master starts the read or write operation and the selected slave responds to the read and write requests.
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AHB : The Advanced High Performance Bus (AHB) was introduced in AMBA 2.0. It is an alternative to ASB where high performance features are required. It supports wider data bus configurations, single-cycle bus master transfer, split transactions, and single clock operations. Just like ASB, AHB bus also requires additional components to manage communication mechanisms such as read multiplexer, write multiplexer, decoder, arbiter, address and control multiplexer. The bus system consists of three signals – address signal, data write bus and data read bus. The address signal is used to select a slave, the write data bus is used to move commands from the master to the slave, and the read data bus is used to move responses from the slaves to the masters. The master accesses the bus by requesting the arbiter and uses the decoder to select a slave. The bus is assigned to a master based on a prioritization scheme. This scheme is defined in the AMBA specifications and differs between different designs. There are 20 different AHB signals in total, compared to 15 signals in ASB.
- AHB-lite : It is a simplified version of AHB. Supports communication mechanisms with a single master without the need for any arbiter. It also excludes some high-performance features of AHB, such as split transactions and retries.
- AXI : Advanced Extensible Interface (AXI) is a point-to-point interconnection specification that overcomes the limitations of shared bus protocols in connecting multiple agents. It was specifically designed to manage communication mechanisms with multi-core processors and controllers. AXI specifications were introduced in AMBA 3.0. Instead of using a system bus, it uses well-defined interfaces for high-bandwidth, low-latency communication mechanisms. It has several improved features compared to AHB, such as multiple pipelined transfers, separate read/write threads, wider data bus widths, and bursty data transfers.
- AXI-lite : It is a simplified version of the AXI protocol. Lacks intermittent data transfer compared to full AXI specifications.
- AXI Streaming : This is a modification of the AXI protocol to support streaming data from masters to slaves. In this protocol, data is only moved in one direction, from master to slave. Read/write channels are not separated in the AXI stream, unlike the full AXI specification. It is possible to transfer multiple data streams between master and slave. This protocol is useful in applications like video streaming, game streaming, etc.
- ACE : The AXI Coherency Extensions (ACE) specifications were introduced in AMBA 4.0. This specification is used to manage communication mechanisms in multi-core processors/controllers with coherent cache memories shared between them. The ACE specification extends the AXI read and write channels by using separate snoop addresses, snoop data channels, and snoop response channels. These additional channels implement eavesdropping-based coherence protocol.
- ACE-lite : ACE-lite is a simplified version of the full ACE specification. It is designed to manage communication mechanisms with agents that do not have their own cache memory, but can still participate in a shareable coherence system using unidirectional coherence. Examples of such agents are DMA controllers and Network-on-Chip blocks.
- CHI : The Coherent Hub Interface (CHI) is a reworking of the ACE protocol for heterogeneous and complex computing systems. The ACE protocol uses signal-level master-slave communication interconnection using a large number of wires and additional channels for eavesdroppers and responses. This works well for small coherent clusters, such as dual- or quad-core mobile SoCs. However, with many heterogeneous components like DSP, GPU, NPU, etc., AXI hits limitations as it is still a signal-based protocol. CHI is a redesign of the AXI bus that uses packet-based interface protocols instead of a signal-based bus system.
Conclusion
If you work in VLSI design, you've probably heard of or learned about AMBA protocols. AMBA has evolved over the years to meet the needs of next-generation SoC designs and future IC developments. AMBA protocols are open standard and can be downloaded from the Arm website after free registration. This article provides an overview of various AMBA specifications. You can download the specs from Arm's website and learn more about these chip design protocols.