Trends toward greater power density and cost optimization dominate the goals of developing efficient, high-power applications that create substantial value for segments such as electromobility.
To overcome these limits, Infineon Technologies announced that it has successfully registered its QDPAK and DDPAK Top Cooling Packages (TSC), which are ideal for high voltage MOSFETs, as a JEDEC standard. This registration further solidifies Infineon's goal of helping establish broad adoption of TSC in new designs with a standard packaging design and footprint.
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Furthermore, this provides flexibility and comfort to OEM manufacturers to differentiate their products in the market and take power density to the next level to support diverse applications.
“As a solutions provider, Infineon continues to influence the semiconductor industry through innovative packaging technologies and manufacturing processes,” said Ralf Otremba, principal engineer, high voltage packaging at Infineon. “Our advanced top-cooled packages bring significant advantages at the device and system levels to meet the challenging demands of cutting-edge high-power designs. Package contour standardization will help alleviate one of the key design concerns of OEMs for high voltage applications by ensuring pin-to-pin compatibility between suppliers.”
For more than 50 years, the JEDEC organization has been a global leader in developing open standards and publications for the microelectronics industry for a wide range of technologies, including package outlines. JEDEC has widely accepted semiconductor packages such as the TO220 and TO247 through-hole (THD) devices – devices that have been used prominently in recent decades and are still an option in new on-board charger (OBC), high voltage (HV) designs. ) and low voltage (LV) DC-DC converters.
The registration of TSC surface-mounted (SMD) packaging designs QDPAK and DDPAK signals a new era for packaging contours, ushering in broad market adoption of TSC technology as a replacement for TO247 and TO220, respectively. With the benefits of this technology, this new entry into the JEDEC family of packages, in accordance with the MO-354 standard, serves as a key enabler for the transition from high-voltage industrial and automotive applications to top-side cooled designs on next-generation platforms. generation.
To ease the design transition for TO220 and TO247 THD device customers, Infineon has designed SMD QDPAK and DDPAK devices to offer equivalent thermal capabilities with improved electrical performance. Based on a standard height of 2.3mm for QDPAK and DDPAK SMD TSC packages for HV and LV devices, developers can now design complete applications such as OBC and DC-DC conversion with all SMD TSC devices measuring the same height. Compared to existing solutions that require a 3D cooling system, this facilitates designs and reduces the cost of the cooling system.
Additionally, TSC packaging offers up to 35% lower thermal resistance than standard bottom side cooling (BSC). By allowing use of both sides of the PCB, TSC packages offer better use of board space and at least twice the power density. Thermal management of packages is also improved by thermal decoupling from the substrate, as the thermal resistance of the conductors is much higher compared to the exposed top of the package.
Due to better thermal performance, it is not necessary to stack different plates. Instead of combining FR4 and IMS, a single FR4 is sufficient for all components and also requires fewer connectors. These features provide a general bill of materials (BOM), which reduces the overall system cost.
In addition to improved thermal and power capabilities, TSC technology also offers an optimized power circuit design for greater reliability. This is possible by placing the drivers, which can be placed very close to the power switch. The low parasitic inductance of the trigger switch circuit reduces circuit parasitics and leads to fewer gate rings, higher performance, and lower risk of failures.
