A field programmable gate array or FPGA is a logic chip that contains a two-dimensional array of programmable cells and switches. Essentially, they are integrated circuits (ICs) that have an array of identical logic blocks with programmable interconnections.
Similar to how you can paint any picture on a blank canvas, an FPGA allows an engineer to design any digital circuit. Just generate and download the bit file and that's it.
This is a significant development compared to conventional microcontrollers, which do not support larger projects. For example, 8051 microcontrollers used Harvard architecture with CISC instruction set. FPGAs do not have these instruction sets built in, providing the designer with greater flexibility.
Another difference: where a microcontroller has its own CPU that starts the controller, holds memory and performs various tasks, an FPGA does not. It cannot start working on its own due to the lack of traditional architecture.
Illustration of a typical FPGA device.
Why FPGAs?
Compared to a microcontroller, FPGAs offer several advantages. As mentioned, they are much more flexible than the limited functionality of controllers. FPGAs also have greater memory capacity.
The main difference between the two is that an FPGA controls the hardware while a microcontroller controls the software. This is why FPGA is typically programmed in hardware descriptive languages (HDLs).
There are technologies similar to FPGA, although with different applications, ports and basic architectures. For example, application-specific integrated circuits (ASICs) are also programmed by HDLs. The difference is that they are designed for a specific application, while FPGAs give you the freedom to run any design.
The advantage of ASICs is that they work faster. But FPGAs can act as ASICs, which is an advantage. FPGAs also have the ability to reprogram in the event of a bug. ASICs cannot do this.
Another similar technology is found in complex programmable logic devices (CPLDs). CPLDs have the characteristics of programmable logic arrays (PALs) and FPGAs.
Here is a comparison between the two:
1. CPLDs have non-volatile memory while FPGAs have volatile memory. This means that when “powered on”, a CPLD retains memory, while an FPGA deletes previous data. This is why an FPGA requires an external ROM. The previous data is then provided to the FPGA when powered on.
2. The main element of a CPLD is a macrocell. A single macrocell consists of several AND gates, a D flip-flop, a multiplexer, and an EX-OR gate. They are connected using a block called a programmable interconnect. The main element of an FPGA is a look-up table or LUT. In a Xilinx device, the LUT is a function generator that can provide 16 × 1 bit synchronous RAM and ROM. Function generators are implemented as 4 input LUTs.
3. A CPLD has about 500 to 12,000 ports, a much smaller number than an FPGA. It has between 3,000 to 5,00,000 gates.
4. The cost of an FPGA is higher than that of a CPLD.
An FPGA is generally preferred, which offers more flexibility with a greater number of ports. These features are important when designing complex circuits.
FPGA architecture
The main blocks of any architecture are configurable logic blocks (CLBs) or logic blocks, interconnect and I/O lines. Here is an illustration of the FPGA:
The architecture of an FPGA.
A CLB is the basic building block of an FPGA. It is a logical cell that can be configured or programmed to perform specific functions. These building blocks are connected to the interconnect block.
A CLB can be implemented using LUT or multiplexer-based logic. In LUT-based logic, the block consists of a look-up table, a D flip-flop, and a 2:1 multiplexer. Flip-flops are used as storage elements. The multiplexer selects the appropriate output.
Each CLB is composed of a certain number of slices. The slices are grouped into pairs and organized into columns. The number of CLBs on a device varies depending on the vendor and device family. For example, Xilinx's Spartan 3E FPGA contains four slices. Each slice is composed of two LUTs and two storage elements.
The function of the LUT is to implement logic, while the dedicated storage elements can be flip-flops or latches. CLBs are organized into a series of rows and columns.
Illustration of an FPGA building block, using a LUT-based CLB.
Illustration of an FPGA building block, using a MUX-based CLB.
The arrangement of CLBs in the Spartan3E FPGA.
The interconnect is the programmable network of signal paths that exist between the inputs and outputs of the functional elements of a device. This is also known as routing.
There are several types of routing, including local routing for interconnection between:
- LUTs
- Flip-flops and general routing matrix
- General-purpose routing for interconnection between rows and columns of CLBs
- I/O routing for pin swapping or blocking purposes
Routing options allow adopting new designs into the existing PCB layout. Other routing methods include dedicated routing sources to improve performance, the distributed global routing clock, and other signals.
A cross-sectional diagram of a direct interconnect technique used in FPGA devices.
Input/output blocks (IOBs) provide unidirectional or bidirectional programmable interfaces between package pins and the device's internal logic.
There are three signals present in an IOB:
1. The input path to carry data from the pad to the respective line.
2. The output path that carries data from the internal logic to the IOB block through a multiplexer and a three-state driver.
3. The three-state path, which determines the high-impedance state of the output driver
All signals come with the inverter option.
A Spartan2 FPGA I/O block.
Distributed and block RAM
Distributed and block RAM are mainly found in Xilinx devices. Most configurable logic blocks or CLBs on a Xilinx device contain a small amount of RAM that is either single or dual port. It is called distributed RAM because it is spread across the FPGA across multiple LUTs.
One disadvantage of distributed RAM is that it cannot be used for larger projects as a single CLB is insufficient. However, it is possible to implement several RAM blocks in parallel to obtain greater memory. The Xilinx synthesizer tool infers which memory type to use based on the code.
Block memory is a dedicated block of dual-port memory, consisting of several kilobytes of RAM. Should be implemented on larger devices. The number of RAM blocks present in an FPGA depends on how advanced it is. For example, the Spartan 6 FPGA has a larger block of RAM than the Spartan 3.
Distributed and block RAM have different modes of operation. Although the WRITE operation for each is synchronous, the READ operation varies. For distributed RAM, data is read directly as soon as it is entered, meaning it does not wait for a clock signal. This means it is asynchronous.
On the other hand, the RAM block operates in a synchronous mode of operation, so data can be written to memory only on the rising edge of the clock.
The implementation style can select any type of RAM using the “ram_style” constraint.
Programming an FPGA
The languages that can be used to program an FPGA are VHDL, Verilog and SystemVerilog.
Very high-speed integrated circuit (VHSIC) hardware description language (VHDL) has all the features that real-life hardware has.
VHDL's key features include:
- A concurrent language, meaning instructions can be implemented in a parallel manner, similar to real-life hardware.
- A sequential language, meaning that instructions are implemented one after the other in a sequence.
- A specific language of time. Signals, like clocks, can be manipulated according to a specific requirement. For example, you can start a process when the clock is on the rising edge, providing suitable delay, reversing the clock, etc.
- It is not case sensitive. The VHDL code is translated into wires and ports that are mapped onto the device.
The different VHDL modeling styles include behavioral, structural, data flow, and a combination of the three.
Combinational and sequential instructions can be used to implement the modeling styles. Sequential instructions are implemented one after the other (serially), while combinational instructions are executed simultaneously (in a parallel manner).
In the behavioral style, only functions are described, typically using the PROCESS statement. The architecture of the registers is not defined.
In the structural type, the circuit is described in terms of interconnected components. For example, a full adder is implemented in terms of two half-adders.
In data flow style, the circuit is described using concurrent instructions. Thus, a MUX could be described in terms of gates, such as EXOR – implemented according to the Boolean expression obtained from the truth table. (Although this is not an ideal way to write code because it has multiple dependencies and uses concurrent statements.)
Mixed modeling styles use any combination of these three styles.
CODE: A behavioral implementation of a 4-bit counter in VHDL
IEEE library;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.display.all;
entity counter is
Port (clk: in STD_LOGIC;
out_count: output STD_LOGIC_VECTOR (3 to 0));
final counter;
accountant's behavioral architecture is
to start
process (clk)
variable count:std_logic_vector(3 to 0):=”0000″;
to start
if(clk'event and clk='1′) then
count:=count+'1′;
if(count=”1111″) then
count:=”0000″;
end if;
end if;
out_count<=count;
end of the process;
final Behavioral;
Schematic of a register transfer level or RTL .
Verilog is also a hardware descriptive language (HDL) typically used to design and verify digital circuits and the register transfer level or RTL (i.e., how data is transformed as it passes from register to register) of abstraction. Thus, it allows projects at various levels of abstraction. It has a syntax similar to C.
An example of how the Verilog language defines hardware in FPGA devices.
Verilog has three levels of abstraction: behavioral, RTL, and gate level.
In behavioral abstraction, a system is described by a concurrent algorithm. In RTL, the system is implemented by transferring data between registers with respect to the clock. At the gate level of abstraction, a system is characterized by time and logical links.
The Verilog system is built by modules and ports. Modules contain multiple components and can consist of instances of other modules. Ports have three types: input, output and input.
Modules include:
1. Parameters: constants with a value specified at compile time.
2. Networks: connect components.
3. Records: serve as storage elements, with values stored during procedural instructions. (Register types are reg, integer, type, and real.)
4. Primitives and instances: predefined module types, such as logic gates.
5. Ongoing work: describe how data moves from one place to another (a network or a registry).
6. Procedural blocks: represent sequential behavior – they are sequences of executable instructions.
7. Task/function definitions: implemented only within a procedural block.
The hierarchy of a Verilog system.
VHDL versus Verilog
VHDL and Verilog languages are equally effective in terms of hardware descriptions. Typically, selection is based on preference, available electronic design automation (EDA) tools, and business, business, and marketing goals.
VHDL allows the compilation of multiple project units to reside in the same file, which is useful when managing large project structures. It is ideal for high-level hardware modeling, offering several libraries.
In terms of data types, VHDL offers a wide choice of data types (user-defined and otherwise). In Verilog, all data types are predefined. Despite this drawback, Verilog data types are easy to use and focus on the hardware modeling aspect rather than the abstract.
In Verilog, a compilation is often used to speed up the simulation. This language is preferred for its simplicity, but it does not offer libraries.
Overall, VHDL is ideal for managing large projects with the help of configuration, generic generation, and packaging. Verilog does not have declarations that help manage large design structures. Verilog exhibits features similar to C without instructions, but is easier for beginners to learn than VHDL.
FPGA Applications
FPGAs are flexible and customizable, making them suitable for a variety of high-end industries such as aerospace, automotive, energy, medical, and defense. For example, multinational technology conglomerate Cisco, which makes networking hardware and software, uses FPGA in its switches and routers to increase hardware speed.
FPGA is also used in portable electronics, digital signal processing (DSP), and radio astronomy, where it offers high-quality computational performance compared to microprocessors or DSPs. They are also found in wireless communication systems, security systems, scientific instruments, and high-performance computing.
In the medical field, FPGAs are currently used in CT scanners, MRIs, ultrasounds, X-ray machines, and surgical systems.
FPGAs offer potential use in nuclear power plants because the systems can be simpler, easier to test, and more reliable than complex software. Additionally, FPGA-based systems are beginning to be used in new plants and I&C (instrumentation and control) projects, as well as in replacements and upgrades of operating plants.
