O que é um design de baixo consumo de energia?

What is low power design?

June 16, 2024 Roberto Magalhães

Low power design is a system that uses a set of techniques and methodologies with the aim of optimizing battery life and reducing overall system power dissipation. To optimize power there are many low power techniques that depend on the level of design selected, ranging from semiconductor technology to the highest levels of abstraction. These abstraction levels are classified as system, algorithm, architecture, circuit, and process levels which we will discuss later in the article and examine some of the information related to reducing power consumption in embedded systems. So, in a future article, we will discuss the features of the microcontroller-based low-power system and how you can use them to extend battery life.

General terms
Before we proceed, we must know these terms:
Current . It is a measure of the amount of electrical charge transferred per unit of time through a closed circuit. The default unit is amps, which is defined as coulombs (a unit of charge) per second.
I=Q/t

Power. Electrical power (P) is the rate at which work is done or energy is transformed in an electrical circuit.
P = VI
Where V is the potential difference in the circuit and I is the electric current that passes through the electrical circuit

Energy . Energy is the ability to do work. If the power is constant over the time interval, then the energy can be expressed simply as
E = Pt

If power consumption is constant, power consumption will be power * time during which energy is consumed. Reducing energy consumption will only save energy if the time required to complete the task does not increase.

Let's understand low-power embedded systems by doing an experiment with LED brightness. Our goal here is to demonstrate how we can drive load with low power using an MCU.

To set up
Here we use an Arduino to control the LED brightness. Arduino provides PWM (Pulse Width Modulation) which can periodically output HIGH and LOW. The PWM function, periodically switching between HIGH and LOW at a specified rate, can be used to adjust the LED brightness.

Fig: 1 Experiment setup

Code explained
To create a PWM signal, we use the analog function Write(x, y) where x is the digital pin and y is a value for the “duty cycle”, between “0 and 255”, where 0 indicates 0% duty cycle and 255 indicates 100% duty cycle, which means when the PWM ratio reaches 255, it is decreased until it reaches 0 to dim the LED gradually.

The duty cycle is the relationship between the time a load or circuit is ON compared to the time the load or circuit is OFF. A 60% duty cycle is a signal that is ON 60% of the time and OFF 40%.

Test 1
When the PWM ratio is 10 and the Duty Cycle is 4%.

Fig: 2 Try with low LED brightness.

The LED's low brightness (10%) uses less drive current, which means less power is consumed. And on 100mA battery with 0.1mA load, the runtime will be 1000 hours.

Figure 3. Signal A with 10% duty cycle

Test 2
When the PWM ratio is 150 and the duty cycle is 58%.

Fig: 4 Experience moderate LED brightness.

Half the LED brightness (58%) uses half the drive current, which means half the power is consumed. On a 100mA battery with a 1.85mA load, the run time will be 54 hours.

Fig.5: Signal A with 58% duty cycle

Test 3
When the PWM ratio is 255 and the duty cycle is 100%.

Fig: 6 Try with full LED brightness.

Full LED brightness (100%) uses all of the unit's current, meaning more power is consumed. On 100mA battery with 3.16mA load, run time will be 31 hours.

Fig. 7: Signal A with 100% duty cycle

The current is proportional to the brightness of the LED. Therefore, the current is lower if the brightness of the LED is lower, which implies that low power consumption will equal low power consumption.

Why do we need low power design?
Embedded systems need to be energy efficient during operation to ensure long battery life, reduce grid power consumption and avoid excessive heat generation. A product's longer battery life can also lead to lower maintenance costs, as costly battery replacement visits occur less frequently. Additionally, portable devices such as cell phones, game consoles, and battery-powered electronic systems require microelectronic circuits designed with ultra-low power dissipation. For example, measurement solutions like automatic meter reading (AMR) require longer battery life and portability as they need to be attached to each meter. They should work for about 8 to 10 years after installation.

Power Optimization Levels
The low-power design of any system is a combination of optimized manufacturer, software, and hardware. In these combinations, power reduction can be implemented at different levels of design abstraction: system, architecture, algorithms, circuit, and process level. The most efficient design decisions derive from choosing and optimizing architectures and algorithms at these levels. Let's briefly discuss these levels at which energy reduction can be incorporated:

Fig. 8: Project Flow Levels

System Level: This level includes power optimization techniques that can be done at the time of IC manufacturing and also at the hardware level. For example, design partitioning is the practice of dividing a system on chip (SoC) into small blocks, which is done by the manufacturer. This allows users to efficiently manage semiconductor designs as a related set of functional blocks. Semiconductor designs are most efficiently managed as related sets of functional blocks.
Algorithmic Level: In this technique, the number of operations that require greater power is reduced, which is basically part of the Software. This approach reduces the number of operations and therefore reduces the number of hardware resources. For example, most DSP (digital signal processing) algorithms involve several multiplication operations. Multiplication is the most power-consuming operation in such algorithms and can be replaced by shift-add operations (this method adds the multiplicand X to itself Y times, where Y denotes the multiplier) to reduce power.
Architectural Level: Measures at the architectural level include intelligent power management of various system blocks, pipeline utilization and parallelism, design of bus structures, and voltage scaling. At this level, power reduction can be done on both the hardware side and the software side. For example, power consumption in CMOS circuits is proportional to capacitance. When designing the PCB, we can minimize the bus length through optimal module placement, which will reduce the capacitance.
Logic/Circuit Design Level: This level includes the power optimization techniques that can be done at the time of manufacturing ICs, hardware and also software. For example, transistor sizing is the process of reducing or increasing the channel width of the transistor at the time of manufacturing. The smaller the transistors, the more transistors can fit on a chip and the faster and more efficient the processor can be. Another example is using a custom design on the hardware side where the components of a circuit used are more static than dynamic.
Process Level: This level includes the power optimization techniques that can be done only on the hardware side of the system. For example, multiple supply voltages are being used in different functional blocks of the core to save power. As another example, reducing the supply voltage from 5.0 to 3.3 volts (a 44% reduction) reduces power consumption by about 56%.

**We will discuss this in detail in a future article.

Power modeling
Power modeling is a technique or procedure for studying the power generated, lost and distributed in a system. It helps in recording past power flow data and preparing future plans and system design. In power modeling, Total Power Dissipation (PT) can be broadly divided into the following:

Fig. 9: Energy Dissipation Model

Static Power Dissipation (PS) : Power consumed during standby mode. (When microcontroller is in sleep mode but LDO (Low Drop Out) is active and consumes power)

Fig. 10: Static energy dissipation

Dynamic Power Dissipation (PD) : Power dissipation during signal switching at the cell input during and discharge of circuit capacitances. Switched capacitance is the main source of dynamic energy consumption and arises from the charging and discharging of capacitors at the circuit outputs.

Fig. 11: Dynamic Power Dissipation

Short-Circuit Power Dissipation (PSC) : It is the secondary source of dynamic power consumption where power is dissipated by an instantaneous short-circuit connection between the supply voltage and ground at the moment the gate changes state , which can cause dissipation of more than 20% of the total energy.
PT = PS + PD + PSC