The demand for greater bandwidth and security in network infrastructure, driven by the growth of hybrid work and the geographic distribution of networks, is redefining borderless networks. Led by AI/ML applications, total port bandwidth for 400G (gigabits per second) and 800G is predicted to grow at an annual rate of more than 50%, according to 650 Group.
This dramatic growth is expanding the transition to 112G PAM4 connectivity beyond just cloud data centers and telecommunications service provider switches and routers to enterprise Ethernet switching platforms.
Microchip Technology is responding to this market shift with the META-DX2 Ethernet PHY (physical layer) portfolio, introducing a new family of META-DX2+ PHYs.
These are industry-first solutions set to integrate 1.6T (terabits per second) of line-rate end-to-end encryption and port aggregation to maintain the most compact footprint in the transition to 112G PAM4 connectivity for enterprise Ethernet switches, devices security systems, cloud interconnection routers and optical transport systems.
“The introduction of four new META-DX2+ Ethernet PHYs demonstrates our commitment to supporting the industry’s transition to 112G PAM4 connectivity powered by our META-DX retimer and PHY portfolio. Together with our META-DX2L retimer, we now offer a complete chipset for all connectivity needs, from reprogramming, gearbox, to advanced PHY functionalities,” said Babak Samimi, Corporate Vice President of Communications Business Unit at Microchip.
Samimi added: “By offering hardware and software compatibility, our customers can leverage architectural designs in their enterprise, data center, and switching and routing systems from service providers who can offer advanced feature enablement on a pay-as-needed basis, including end-to-end complete security, multi-rate port aggregation, and accurate timestamping through a software subscription model.”
META-DX2+'s configurable 1.6T data path architecture outperforms next-gen competitors by 2x in total gearbox capacity and 2:1 bump-free protection switch mux modes enabled by its unique ShiftIO capability. XpandIO's flexible port aggregation capabilities optimize router/switch port utilization when supporting low-rate traffic.
Additionally, the devices include IEEE 1588 Class C/D Precision Time Protocol (PTP) support for nanosecond-accurate timestamping required for 5G and critical enterprise services. By offering a portfolio of footprint-compatible retimers and advanced PHYs with encryption options, Microchip enables developers to expand their designs to add MACsec and IPsec based on a common board design and Software Development Kit (SDK).
META-DX2+’s distinctive features include:
- Dual 800 GbE, quad 400 GbE and 16x 100/50/25/10/1 GbE MAC/PHY
- Built-in 1.6T MACsec/IPsec engines that offload encryption from packet processors so systems can more easily scale to higher bandwidths with end-to-end security
- Board savings of over 20% compared to competing solutions that require two devices to provide the same 1.6T gearbox and impact-free 2:1 mux modes
- XpandIO enables aggregation of low-rate Ethernet client ports into high-speed Ethernet interfaces optimized for enterprise platforms
- ShiftIO capability combined with a highly configurable integrated crosspoint enables flexible connectivity between external switches, processors and optical systems
- Device variants with 48 or 32 Long Reach (LR) capable 112G PAM4 SerDes, including programmability to optimize power versus performance
- Support for Ethernet, OTN, Fiber Channel and proprietary data rates for AI/ML applications
“As the industry transitions to a 112G PAM4 serial ecosystem for high-density routers and switches, line-rate encryption and efficient use of port capacity become increasingly important,” said Alan Weckel, founder and technology analyst at 650 Group, LLC. “Microchip’s META-DX2+ family will play an important role in enabling MACsec and IPsec encryption, optimizing port capacity with port aggregation, and flexibly connecting routing/switching silicon to 400G and 800G multi-rate optics.”
Like the META-DX2L retimer, the new META-DX2+ series of PHYs can be used with Microchip's PolarFire FPGAs, the ZL30632 high-performance PLL, oscillators, voltage regulators, and other components that have been pre-validated as a system for help speed projects into production.