Key factors for optimizing power consumption in an embedded device

In the previous article, we learned what a low-power system is, so now we will talk about the main factors with which we can create a low-power embedded system design.

The energy-efficient embedded system is comprised of hardware and software design along with proper selection of components. Optimization is achieved by efficient implementation at different stages using different techniques. The available techniques are given below.

Higher levels of power reduction techniques include system, algorithm, and architectural levels, as well as lower levels of power reduction techniques, including circuit and process level. Higher levels provide greater amounts of power reduction for chip designs, giving designers a greater degree of freedom to implement low-power design techniques (up to 70% reduction). Consequently, the power optimization process is the most effective method for higher levels of abstraction. Let's learn more about these levels in detail.

System level
The system level generally includes the techniques that can be implemented during custom IC manufacturing or hardware design. The system level techniques are as follows:

• Hardware/software partitioning. Mapping a system level into specific hardware (FPGA, ASIC, etc.) and software (code running on CPU, MCU, etc.) components based on your requirements.
• Task characterization. This step helps in developing a low-power implementation strategy to characterize tasks according to processing frequency, processing time, and hardware algorithm alternatives. This is important because implementation strategies will depend heavily on these characteristics.

Algorithmic level
The most effective design decisions derive from choosing and optimizing algorithms at the highest levels. This technique is used at this level where the number of operations that require greater power is reduced. This approach also reduces the number of switching activities, which leads to a decrease in the switched capacitance of the entire system, thus reducing the dynamic power consumption of the system. For example, the arithmetic or register units of a microprocessor will work only when such logical commands are invoked, so we can disable logical commands that are not in use during a given clock cycle.

Architectural level
Different architectural-level techniques are applied to minimize dynamic power dissipation in arithmetic circuits, especially in digital multipliers. Some of the architectural level techniques are:

• Parallelism. The simultaneous execution of multiple programs or multiple blocks of a program is known as parallel processing. Parallelism can be done by multi-core architecture. By replicating the same core multiple times, the received inputs are applied to different cores in sequence.
• Voltage scale. In this technique, the overall operating voltage of the device is kept low for the entire board as the power consumption is directly proportional to the operating voltage. For example, if all chips can run at 2.7V, you would maintain a 1V margin and set that voltage to the board. When the processor supply voltage is reduced, the system speed decreases. To complement this, software techniques such as pipelines can be used to maintain the system throughput explained in the software techniques.
• Pipeline. The process of accumulating processor instructions through a pipeline. Allows you to store and execute instructions in an ordered process. The pipeline does not reduce power by itself, but instead reduces critical path delay by inserting registers between combinational logic. The pipeline also reduces instructions per clock cycle (IPC), due to high branch misprediction penalties and other dangers, and thus can reduce energy efficiency. Pipeline timing slack can be used for voltage scaling and gate reduction to achieve significant power savings.

Logic and circuit level
The logic and circuit levels often include techniques that can be implemented during custom IC manufacturing or in hardware and software design. Some of the logic and circuit level techniques are:

• Transistor sizing. The process of reducing or increasing the transistor channel width at the time of manufacturing. The smaller the transistors, the more transistors can fit on a chip and the faster and more efficient the processor can be. For example, if the transistor size is 25 μm, the drive current will be only 0.9 mA and if the size is 100 μmk, the drive current will be 20 mA.
• Clock control. A technique used in many synchronous circuits to reduce dynamic power dissipation by removing the clock signal when the circuit is not in use. This can be achieved by adding Enable Circuit which will cycle through clock usage when Enable is high and vice versa. These circuits can be a gate, three-state buffer, latch, etc.

Process/Technology Level

Threshold voltage . The reduction of voltage oscillation (oscillation is the difference between the maximum output voltage and the minimum output voltage) and the reduction of the effective load capacitance (sum of the load capacitance and the parasitic capacitance), reducing energy dissipation. Additionally, reducing VDD on non-critical paths will help reduce power consumption.

Component selection

• Use of more static than dynamic circuits, as the static power loss is much smaller in a dynamic logic circuit.
• Selecting the correct input voltage for the embedded board is important whether we are using a battery or an adapter for the power supply. For example, if all circuits on the board are powered by 5V or 3.3V, using a 5V – 6V power input is better than using a 12/24V DC input or battery input.
• Booster circuits are generally inefficient. If you have the option to use buck conversion, use buck instead of boost.
• The quiescent current of a power supply is the amount of current that is drawn at zero load or no load. Always use a low quiescent current power supply as it has very high efficiency over the range of current your circuit will draw.

Circuit Design Level The designer has several options when designing a low-power system, including the following:

• Choose low-power components in the design. For example, when selecting an IC, consider an IC with low power consumption (active/idle) and low operating voltage.
• Optimize PCB size so that you can minimize power consumption of electronic circuits.
• Positioning the component so that the signal track length can be minimized and the signal propagation time is as fast as possible to minimize any power loss.

Benefits of Low Power Embedded System Design

• A low power system produces less amount of heat, which is good for the environment.
• The duty cycle of the embedded system is improved due to lower power dissipation.
• The low energy consumption system also helps to reduce the production cost as these systems will be simpler and more economical.

Conclusion
Successful design and evaluation of an embedded system requires proper power management. In this article, we review most design levels where power reduction techniques can be incorporated.