In the previous tutorial, different types of records were discussed. Registers and counters are two types of sequential circuits that are built exclusively from flip flops . Counters are those registers that go through pre-determined sequences of states when applying input pulses. Input pulses can come from a master clock or some external source. They can be applied to the counter at regular intervals or randomly. There are two types of counters – asynchronous counter (also known as ripple counter) and synchronous counter.
The sequence of states in a counter can be binary numbers or any other sequence of states. Counters that follow the binary number sequence are called binary counters. Binary counters are again categorized as Up Counter, Down Counter, and Up/Down Counter. Ripple and Synchronous counters can be used as binary counters. There are many other types of counters that follow different sequences of states other than binary numbers, such as BCD counter, ring counter, Johnson counter, etc.
Asynchronous/ripple counter –
In asynchronous counter or Ripple, the input pulse is applied to a flip-flop or some flip-flops of the counter and its output drives the other flip-flops one after the other. Therefore, all flip-flops of a ripple counter do not share a common clock pulse; instead, the clock pulse is applied to just one or a few flip-flops.
This is the simplest counter in terms of logical operation and therefore the easiest to design. In this counter, all flip-flops do not share a common clock signal. The clock pulse is applied to the first flip-flop. that is, the least significant bit stage of the counter and the successive flip-flop are driven by the output of the previous one, and therefore the counter has a cumulative settling time. Consequently, its operating speed is limited.
The first stage of the counter thus switches first on applying a clock pulse to the first flip-flop and the successive stage changes its states in turn causing a 'ripple effect' of the counting pulses. As the triggers move across the flip-flops like a ripple, this type of counter is called a ripple counter. The ripple counter can be a binary counter (if it follows the binary number sequence) or it can be constructed to follow another sequence of states, such as the BCD ripple counter follows the BCD number sequence.
Synchronous Counter –
In synchronous counters, a common clock pulse is applied to the inputs of all flip-flops. All flip-flops are driven by the common clock pulse simultaneously. In this case, the change in the state of a flip-flop is determined by inputting data into it, rather than applying the clock pulse. The clock pulse is generally generated from a master clock on a periodic basis. Synchronous counters can also be constructed to follow the binary number sequence, as in the binary synchronous counter, or another sequence of states, such as the BCD numbering system, in the case of the BCD synchronous counter.
Types of binary counters –
Binary counters follow a sequence of binary numbers. Depending on the way the counting progresses, ripple and synchronous binary counters are classified as follows –
1) Ascending counter – The ascending counter advances the count in ascending order of binary numbers. Counting usually starts at 0 and progresses to a fixed binary number. An n-bit increasing counter can count up to 2n binary numbers. For example, an 8-bit binary counter can count from 0 to 255.
2) Down counter – The down counter advances the count in descending order of binary numbers. The count starts from a fixed binary number and progresses down to 0. An n-bit countdown counter can count down 2n binary numbers. For example, an 8-bit binary countdown counter can count down from 255 to 0.
3) Ascending/descending counter – The ascending/descending counter is constructed by combining ascending and descending counters. In the up/down counter, a mode control input (M) is provided to select the up or down mode. The mode control input involves a combinational circuit that is used between each pair of flip-flops to select count up or count down mode. An n-bit up/down counter can count up or down 2n binary numbers. For example, an 8-bit binary up/down counter can count increasing or decreasing binary numbers in the range 0 to 255.
Binary Ripple Ascending Counter –
A Binary Ripple Up counter progresses through states by counting binary numbers in ascending order. Making this counter is very simple and can be designed by simply applying clock pulse to a flip-flop and cascading the output to the next flip-flop. Subsequent flip-flops in the counter are cascaded in a similar way. A 2-bit ripple counter constructed using toggle (T) flip-flops is shown below –
Figure 1: Ripple Binary Up Counter Logic Gate Diagram
The JK flip-flop can also be used in place of the T flip-flops in constructing this counter by connecting the J and K inputs permanently to logic 1. In the 2-bit rising ripple counter shown above, the external clock is applied to the input flip-flop clock rate. -flop A and output QA are applied to the clock input of the next flip-flop i.e. Flip Flop – B. This 2-bit ripple counter counts from 00 to 11. Its operation can be summarized by the following table of functions –
Fig. 2: Ripple Binary Up Counter Truth Table
From the function table, it can be seen that initially both flip flops are in the reset state. So initially, Q B P A = 00. Now the first negative clock edge is applied to the flip-flop A clock input. As soon as the first negative clock edge is applied, flip-flop A is toggled and QA becomes - if equal to 1. QA is connected to the flip-flop clock input – B. As QA changed from 0 to 1, it is treated as the positive transition of the flip-flop clock B. There is no change in QB because flip-flop finger B is a negative edge driven flip flop . Thus, after applying the first clock pulse, QBQA = 01.
Then the second negative clock edge is applied to the clock input of flip-flop A. On arrival of the second negative clock edge, flip-flop A toggles again and QA is reset to 0. The change in QA acts as a negative clock transition. to flip-flop B. Therefore, it also toggles and QB is set to 1. Therefore, after applying the second clock pulse, QBQA = 10. Then the third negative clock edge is applied to the clock input of the flip-flop A. Upon arrival of the third negative clock transition, flip-flop A toggles again and QA is set to 1 of 0. As this is a positive shift, flip-flop B does not respond to it and remains inactive. Therefore, QB does not change and remains equal to 1. Therefore, after the application of the third clock pulse, QBQA = 11. On arrival of the fourth negative clock edge, flip-flop A toggles again and QA is set to 1 from of 0. This negative change in QA acts as clock pulse for flip-flop B. Hence, it switches QB from 1 to 0. Therefore, after the fourth clock pulse, QBQA = 00.
Binary ripple up/down counter –
In the up/down ripple counter, all flip-flops operate in toggle mode. Therefore, T flip-flops or JK flip-flops are used for its construction. The LSB flip-flop receives the clock directly. But the clock for all other flip-flops is taken from the output of the previous flip-flop. The counter has mode control input (M). Depending on the current state of the mode control input, count up or count down mode is selected. The counter operates in the following two modes –
1) Count up mode (in case of M=0) − The Q output of the previous flip-flop must be connected to the clock of the next stage for the count up to be achieved. To select this mode, the mode selection input M must be at logic level 0 (i.e. M=0).
2) Countdown mode (in case M=1) − If the mode control input is set to 1, then the Q bar output of the previous flip-flop will be connected to the next FF. This will operate the counter in countdown mode.
For example, consider a 3-bit binary up/down ripple counter. As it is a 3-bit ripple counter, its construction requires 3 flip-flops. There is a mode control input which is essential for controlling the selection of count up or count down mode. For a ripple counter, the Q output of the previous flip-flop is connected to the clock input of the next one. Whereas, for a ripple descending counter, the Q-bar output of the previous flip-flop is connected to the clock input of the next one. The 3-bit ripple up/down counter has the following circuit diagram –
Figure 3: Ripple Binary Up and Down Counter Logic Gate Diagram
The selection of the Q and Q bar output of the previous flip-flop will be controlled by the M mode control input so that if M = 0, the count up mode will be selected. Therefore, Q is connected to CLK. If M = 1, countdown mode is selected. Therefore, the Q bar is connected to the CLK. A 3-bit up/down ripple counter can be represented by the following block diagram –
Figure 4: Ripple Binary Up and Down Counter Block Diagram
The operation of this counter can be represented by the following function table –
Fig. 5: Ripple Binary Up Down Counter Truth Table
From the function table, it can be seen that when the mode control input (M) is 0, the count up mode is selected. If M = 0 and M bar = 1, then AND gates 1 and 3 are enabled, while AND gates 2 and 4 are disabled. Therefore Q A is connected to the clock input of Flip Flop B and Q B is connected to the clock input of Flip Flop C. These connections are the same as the normal up counter. Therefore, with M = 0 the circuit works like an increasing counter. When the mode control input is 1, the countdown mode is selected. If M = 1, then AND gates 2 and 4 are enabled, while AND gates 1 and 3 are disabled. Therefore Q Bar is connected to the clock input of Flip Flop B and Q B Bar is connected to the clock input of Flip Flop C. These connections form a countdown counter. Thus, with M = 1 the circuit works like a decreasing counter.
Ripple BCD Counter –
BCD counter, also known as decimal counter, counts BCD numbers from 0 to 9. Since BCD numbers are 4-bit numbers, four flip-flops are required to design a BCD counter. The counter follows a sequence of 10 states and counts from 0 (0000) to 9 (1001) returning to 0 (0000). Multiple BCD counters can be connected in series to represent a larger decimal number. In this case, a BCD counter for each positional weight must be connected to the circuit.
A BCD counter can be constructed using JK flip-flops. To design a BCD counter, four flip-flops are required. These flip-flops can be represented by their binary weights as Q1, Q2, Q4 and Q8. The J and K inputs of the flip-flops are permanently connected to logic 1 or the outputs of other flip-flops. The output of flip-flop Q1 is connected to the clock input of both flip-flops Q2 and Q8. The output of flip-flop Q2 is connected to the clock input of flip-flop Q4. The BCD counter built from JK flip-flops has the following logic gate diagram –
Figure 6: Ripple BCD Counter Logic Gate Diagram
The counter progresses by counting from Q8Q4Q2Q1 = 0000 to Q8Q4Q2Q1 = 1001. The operation of the counter can be summarized by the following table of functions –
Fig. 7: Ripple BCD counter truth table
Synchronous up counter –
Binary rising counter can also be designed as synchronous counter. The synchronous binary up counter has a common clock signal and the sequence of states depends on the data input to the flip-flops. For example, to design a 2-bit synchronous counter, two flip-flops are required. Let the flip-flop that stores LSB be A and the flip-flop that stores MSB be B. The JA and KA inputs of flip-flop A are tied to logic 1. Therefore, flip-flop A works as a flip-flop alternated. The JB and KB inputs are connected to the QA. The 2-bit synchronous binary up counter has the following logic diagram –
Figure 8: Synchronous binary up counter logic gate diagram
Initially, both flip-flops are in the reset state. Therefore, initially, QBQA = 00. When the first negative clock edge is applied, Flip Flop A is toggled and QA changes from 0 to 1. But at the instant of applying the negative clock edge, QA = JB = KB = 0 Therefore, Flip Flop B does not change its state. Therefore, QB remains 0. Therefore, after applying the first clock pulse, QBQA = 01. When the second negative clock edge is applied, Flip Flop A toggles again and QA changes from 1 to 0. But at this instant QA remained 1 .So JB = KB= 1 and Flip Flop B is toggled. Hence, QB changes from 0 to 1. Therefore, after applying the second clock pulse, QBQA = 10.
When the third negative clock edge is applied, Flip Flop A switches from 0 to 1, but there is no state change for Flip Flop B. Therefore, after the third clock pulse is applied, QBQA = 11. When the fourth negative clock transition is applied, QA changes from 1 to 0 as QB also changes from 1 to 0. Therefore, after applying the fourth clock pulse, QBQA = 00. The working of 2-bit synchronous binary up counter can be summarized by the following function table –
Fig. 9: Synchronous binary up counter truth table
Synchronous up/down counter –
A synchronous countdown counter can be constructed using T flip-flops by connecting complementary outputs instead of normal outputs as in the case of up counter. An up/down counter can be constructed by placing a combinational circuit between each flip-flop to determine the counting mode. The combinational circuit can be designed using AND gates and providing an additional mode control input (M) similar to what is done in the case of Ripple Up/Down Counter.
Synchronous BCD counter –
Again, a BCD counter can be constructed as a synchronous counter. To build a synchronous BCD counter, the current and past states of the flip-flops need to be considered. The synchronous BCD counter follows the function table below –
Fig. 10: Truth table of the synchronous BCD counter
In the above function table, the synchronous BCD counter has the following logic gate diagram –
Figure 11: Synchronous BCD counter logic gate diagram
The BCD counter is also called the decade counter. The counter counts BCD numbers from 0 (0000) to 9 (1001). Since BCD numbers are 4 bits long, four flip-flops are required to design the BCD counter. The synchronous BCD counter has all flip-flops sharing a common clock pulse.
Touch counter –
The ring counter is used to generate timing signals. Timing signals are necessary to control operations in a digital system. The ring counter is a circular shift register in which only one flip-flop is set at a time while all others remain zero. In this counter, a single bit is shifted from one flip-flop to another, producing a sequence of timing signals. For example, to produce four timing signals in a digital system, a 2-bit counter combined with a decoder circuit can be used as a ring counter. The ring counter will have flip-flops storing bits in the following sequence – 1000, 0100, 0010, 0001 and 1000.
Accountant Johnson –
An n-bit ring counter shifts a single bit through the flip-flops generating n number of sequence states. The number of states in a ring counter can be doubled by connecting flip-flops in the ring counter in a switch-tail manner. This can be done by connecting the output of one flip-flop with the next. This is called the Johnson Counter. It has the following logic gate diagram –
Figure 12: Johnson counter logic gate diagram
The operation of the Johnson counter can be summarized by the following table of functions –
Fig. 13: Johnson Counter Truth Table
In the next tutorial, discussions related to digital memory will be made.